`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/06/16 21:31:06
// Design Name: 
// Module Name: decoder4to16
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
//din[0] is the highest priority
module Pencoder16to4(
    input [15:0] din,
    output reg [3:0] dout,
    output dinnonzero
);

always @(*)
    begin
        if(din[0]==1'b1)        dout=4'b0000;
        else if(din[1]==1'b1)   dout=4'b0001;
        else if(din[2]==1'b1)   dout=4'b0010;
        else if(din[3]==1'b1)   dout=4'b0011;
        else if(din[4]==1'b1)   dout=4'b0100;
        else if(din[5]==1'b1)   dout=4'b0101;
        else if(din[6]==1'b1)   dout=4'b0110;
        else if(din[7]==1'b1)   dout=4'b0111;
        else if(din[8]==1'b1)   dout=4'b1000;
        else if(din[9]==1'b1)   dout=4'b1001;
        else if(din[10]==1'b1)  dout=4'b1010;
        else if(din[11]==1'b1)   dout=4'b1011;
        else if(din[12]==1'b1)   dout=4'b1100;
        else if(din[13]==1'b1)   dout=4'b1101;
        else if(din[14]==1'b1)   dout=4'b1110;
        else if(din[15]==1'b1)   dout=4'b1111;
        else dout=4'b0000;
    end
assign dinnonzero=|din;
endmodule

module Pencoder4to4(
    input [3:0] din,
    output reg [3:0] dout,
    output dinnonzero
);

always @(*)
    begin
        if(din[0]==1'b1)        dout=4'b0001;
        else begin 
            if(din[1]==1'b1)   dout=4'b0010;
                else begin
                    if(din[2]==1'b1)   dout=4'b0100;
                    else begin 
                        if(din[3]==1'b1)   dout=4'b1000;
                        else dout=4'b00;
                        end
                end
        end
    end
assign dinnonzero=|din;
endmodule

module byte_shfnum(
    input [1:0] dest,
    input [1:0] src,
    output reg [1:0] dout
    );
    always @(*)   //It includes all Inputs. You can use this instead of specifying all inputs in //sensivity list.Verilog-2001 Feature
    begin
       case ({dest,src})
       4'b0000 : dout = 2'h0;
       4'b0001 : dout = 2'h3;
       4'b0010 : dout = 2'h2;
       4'b0011 : dout = 2'h1;

       4'b0100 : dout = 2'h1;
       4'b0101 : dout = 2'h0;
       4'b0110 : dout = 2'h3;
       4'b0111 : dout = 2'h2;
       
       4'b1000 : dout = 2'h2;
       4'b1001 : dout = 2'h1;
       4'b1010 : dout = 2'h0;
       4'b1011 : dout = 2'h3;

       4'b1100 : dout = 2'h3;
       4'b1101 : dout = 2'h2;
       4'b1110 : dout = 2'h1;
       4'b1111 : dout = 2'h0;
       endcase
    end
endmodule
module Pdecoder2to4(
    input [1:0] din,
    output reg [3:0] dout
    );
    always @(*)   //It includes all Inputs. You can use this instead of specifying all inputs in //sensivity list.Verilog-2001 Feature
    begin
       case ({din})
       2'b00 : dout = 4'b0000;
       2'b01 : dout = 4'b0001;
       2'b10 : dout = 4'b0011;
       2'b11 : dout = 4'b0111;
       endcase
    end
endmodule

module decoder2to4(
    input [1:0] din,
    output reg [3:0] dout
    );
    always @(*)   //It includes all Inputs. You can use this instead of specifying all inputs in //sensivity list.Verilog-2001 Feature
    begin
       case ({din})
       2'b00 : dout = 4'h1;
       2'b01 : dout = 4'h2;
       2'b10 : dout = 4'h4;
       2'b11 : dout = 4'h8;
       endcase
    end
endmodule

module decoder3to8(
    input [2:0] din,
    output reg [7:0] dout
    );
    always @(*)   //It includes all Inputs. You can use this instead of specifying all inputs in //sensivity list.Verilog-2001 Feature
    begin
       case ({din})
       3'b000 : dout = 8'b0000_0001;
       3'b001 : dout = 8'b0000_0010;
       3'b010 : dout = 8'b0000_0100;
       3'b011 : dout = 8'b0000_1000;
       3'b100 : dout = 8'b0001_0000;
       3'b101 : dout = 8'b0010_0000;
       3'b110 : dout = 8'b0100_0000;
       3'b111 : dout = 8'b1000_0000;
       endcase
    end
endmodule

module decoder4to16(
    input [3:0] din,
    output reg [15:0] dout
    );
    always @(*)   //It includes all Inputs. You can use this instead of specifying all inputs in //sensivity list.Verilog-2001 Feature
    begin
       case ({din})
       4'b0000 : dout = 16'h1;
       4'b0001 : dout = 16'h2;
       4'b0010 : dout = 16'h4;
       4'b0011 : dout = 16'h8;
       4'b0100 : dout = 16'h10;
       4'b0101 : dout = 16'h20;
       4'b0110 : dout = 16'h40;
       4'b0111 : dout = 16'h80;
       
       4'b1000 : dout = 16'h100;
       4'b1001 : dout = 16'h200;
       4'b1010 : dout = 16'h400;
       4'b1011 : dout = 16'h800;
       4'b1100 : dout = 16'h1000;
       4'b1101 : dout = 16'h2000;
       4'b1110 : dout = 16'h4000;
       4'b1111 : dout = 16'h8000;
       endcase
    end
endmodule

module decoder5to32(
    input [4:0] din,
    output [31:0] dout
    );
    wire [15:0] dlow;
    decoder4to16 DLOW(din[3:0],dlow);
    assign dout=(din[4]==0)?{16'b0,dlow}:{dlow,16'b0};
endmodule

module lzcount4(
    input [3:0] din,
    output reg [2:0] dout
    );
    always @(*)   //It includes all Inputs. You can use this instead of specifying all inputs in //sensivity list.Verilog-2001 Feature
    begin
       case ({din})
       4'b1000 : dout = 3'd0;
       4'b1001 : dout = 3'd0;
       4'b1010 : dout = 3'd0;
       4'b1011 : dout = 3'd0;
       4'b1100 : dout = 3'd0;
       4'b1101 : dout = 3'd0;
       4'b1110 : dout = 3'd0;
       4'b1111 : dout = 3'd0;
       
       4'b0100 : dout = 3'd1;
       4'b0101 : dout = 3'd1;
       4'b0110 : dout = 3'd1;
       4'b0111 : dout = 3'd1;
       
       4'b0010 : dout = 3'd2;
       4'b0011 : dout = 3'd2;
       
       4'b0001 : dout = 3'd3;
       4'b0000 : dout = 3'd4;
       endcase
    end
endmodule